1. Field of the Invention
The present invention relates to the fabrication of semiconductor structures, and more particularly to methods for planarizing patterned conductors using a pre-mask checkerboarding of wiring lines.
2. Background Art
Planarization methods in the fabrication of semiconductor devices are disclosed in U.S. Pat. No. 5,278,105 issued Jan. 11, 1994 to Eden et al. entitled SEMICONDUCTOR DEVICE WITH DUMMY/FEATURE IN, ACTIVE LAYERS that discloses a design and fabrication method for a semiconductor device that allows different types of devices to be processed using the same process steps.
U.S. Pat. No. 5,292,689 issued Mar. 8, 1994 to Cronin et al. entitled METHOD FOR PLANARIZING SEMICONDUCTOR STRUCTURE USING SUBMINIMUM FEATURES discloses a method for fabricating planarized semiconductor structures that are prepared using a plurality of subminimum polysilicon vertical pillars by chemical vapor deposition to prevent depressions in the planarized surface.
U.S. Pat. No. 5,539,240 issued Jul. 23, 1996 to Cronin et al. entitled PLANARIZED SEMICONDUCTOR STRUCTURE WITH SUBMINIMUM FEATURES also discloses planarized semiconductor structures having subminimum vertical pillars to prevent depressions in the planarized surface.
The IBM Technical Disclosure Bulletin, Vol. 26, No. 10A, March 1984 at page 4995 by W. M. Goubau entitled PLANARIZATION OF CONDUCTING SURFACES discloses a planar coating technique using a wiring pattern with evenly spaced, space-filling conductors.